The standard cell of static RAM (Static Random Access Memory) being currently used consists of four transistors and two load resistors, and is constituted as shown in FIG. 1. Referring to FIG. 1, it comprises two pairs each of a MOS transistor and high resistor, (R1,T1) and (R2,T2), which are connected in series between a source supply voltage Vcc and a ground voltage Vss, respectively. Each node point 1,2 between the high resistors and the MOS transistors are respectively connected in cross to each gate 3,4 of the opposite one of MOS transistors T2,T1. Other MOS transistors T3,T4 whose gates are connected to a word line WL are interconnected between said node points 1,2 and bit lines BL and BL, respectively. The transistor gates 3,4 used in the static RAM are conventionally made of silicide or the polycide structure in which a silicide is formed on the polycrystalline silicon layer, and the load resistors R1,R2 are made of the polycrystalline silicon.
The prior method of contacting the silicide gate with the polysilicon resistor is as follows. At first, a gate is formed and an insulating layer is deposited over all the surface of the substrate in which the gate is formed. Then a contact window is formed in the insulating layer and a polysilicon layer is deposited thereon, in sequence. However, the ability to achieve the correct ohmic contact therein greatly depends upon the deposition condition of the polysilicon, wherein the failure in achieving such correct ohmic contact often results in the formation of very high resistance more than dozens of kilo-ohms, even though the polysilicon is deposited on a very clean silicide surface in which the insulating layer is completely etched at the process of forming the contact window. When the contact resistance between the silicide and the polysilicon becomes very high, there arises a problem that said contact resistance limits the current which flows through the load resistors R1,R2 from the source supply voltage Vcc. Therefore, it leads to a failure in compensating for leakage current through the transistors T1 to T4, which often results in data error the memory state.